CHENNAI, India--(BUSINESS WIRE)--RISC-V Foundation:
WHAT: RISC-V Workshop in Chennai, India
WHERE: IC&SR Building, Indian Institute of Technology (IIT) Madras, Sardar Patel Road, Opposite to C, L.R.I, Adyar, Chennai, Tamil Nadu 600036, India
WHEN: Wednesday, July 18 and Thursday, July 19, 2018
DETAILS: The RISC-V Workshop in Chennai will showcase the expansive RISC-V ecosystem, highlighting current and prospective projects and implementations that influence the future evolution of the RISC-V instruction set architecture (ISA). IIT Madras is hosting the event and the lead sponsor is Western Digital.
Western Digital’s Vivek Tyagi, director of business development, embedded and enterprise in India, will present the keynote on Wednesday, July 18. The event will feature a variety of speaking sessions, along with poster presentations and demonstrations. In addition, there will be a panel concluding the first day of the Workshop. The event schedule is as follows:
Wednesday, July 18, 2018:
RISC-V ISA & Foundation Overview
When: 9 a.m. – 9:15 a.m. IST
Who: Rick O’Connor, RISC-V Foundation
RISC-V ISA: Understanding Limitations and Methods to Improve Code Density & Performance
When: 9:15 a.m. – 9:30 a.m. IST
Who: Gnanasekar Rajakumar and Ravikumar Gaddam, Western Digital
Going Beyond the RISC-V General Purpose Solutions
When: 9:30 a.m. – 10 a.m. IST
Who: Neel Gala, InCore Semiconductors
Architecture Exploration of RISC-V Processor and Comparison With ARM Cortex A53 and A72
When: 10 a.m. – 10:30 a.m. IST
Who: Karthikeyan Sugumaran and Tom Jose, Mirabilis Design
It's Not About the Core, It's About the System
When: 11 a.m. – 11:30 a.m. IST
Who: Gajinder Panesar, UltraSoC
RiTA: RISC-V Trace Analyzer
When: 11:30 a.m. – 11:45 a.m. IST
Who: Anmol Sahoo, IIT Madras and Neel Gala, InCore Semiconductors
Keynote: RISC-V: Enabling a New Era of Open Data-Centric Computing Architectures
When: 11:45 a.m. – 12:10 p.m. IST
Who: Vivek Tyagi, Western Digital
Accelerating the RISC-V Revolution: Unleashing Custom Silicon with Revolutionary Design Platforms and Custom Accelerators
When: 13:30 p.m. – 14:00 p.m. IST
Who: Huzefa Cutlerywala, Open Silicon
Mi-V RISC-V Embedded Ecosystem
When: 14:00 p.m. – 14:15 p.m. IST
Who: Krishnakumar Ranamoorthi, Microsemi
Verification of the PULPino SoC Platform Using UVM
When: 14:15 p.m. – 14:30 p.m. IST
Who: Mahesh R. and Shamanth HK, Cisma Consultants
Porting Graphical Stacks to RISC-V Using QEMU and Yocto
When: 14:30 p.m. – 14:45 p.m. IST
Who: Alistair Francis, Western Digital
Panel: Evolving a RISC-V based Ecosystem in India
When: 15:15 p.m. – 16:15 p.m. IST
Who: Vivek Tyagi, Sandisk Western Digital; Konala Varma, Intel; Mahesha Nanjundaiah, HPE; Asutosh Upadhyay, Axilor Ventures; Gunamani Rajagopal, HCL Technologies
Poster / Demonstration Previews
When: 16:15 – 17:00 p.m. IST
Evening Reception, Poster Sessions and Demonstrations
When: 17:00 – 20:00 p.m. IST
Thursday, July 19, 2018
RISC-V Software Development Methodology for RISC-V Devices with RTOS and Linux or Both
When: 9 a.m. – 9:30 a.m. IST
Who: Kevin McDermott, Imperas Software
Linux Kernel on RISC-V: Where Do We Stand?
When: 9:30 a.m. – 10 a.m. IST
Who: Atish Patra and Damien Le Moal, Western Digital
A Comprehensive Framework for Power-based Side-channel Leakage Evaluation of Shakti C-Class
When: 10 a.m. – 10:30 a.m. IST
Who: Muhammad Arsath and Chester Rebeiro, IIT Madras
RISECREEK: From RISC-V Spec to 22FFL Silicon
When: 11:00 a.m. – 11:30 a.m. IST
Who: Vinod Ganesan and Gopinathan Muthuswamy, IIT Madras
Shakti M-Class Libre RISC-V SoC
When: 11:30 a.m. – 12:00 p.m. IST
Who: Luke Leighton, Independent Software Libre Engineer and Advocate
SLSV : The Shakti LockStep Verification Framework
When: 12 p.m. – 12:30 p.m. IST
Who: Paul George, Shiv Nadar University and Lavanya Jagan, IIT Madras
A Survey of E31 RISC-V Core Floor-Plan and Its Impact on Power, Performance and Area (PPA)
When: 14:00 p.m. – 14:30 p.m. IST
Who: Kunal Ghosh and Anagha Ghosh, VLSI System Design Corporation
Integrating Gen-Z in Server-Class RISC-V Processors
When: 14:30 p.m. – 15:00 p.m. IST
Who: Mohan Pathasarathy, HPE
Formal Specification of the RISC-V Instruction Set Architecture
When: 15:00 p.m. – 15:30 p.m. IST
Who: Rishiyur Nikhil & Niraj Sharma, Bluespec
RISC-V Workshop Chennai Conclusion
When: 15:30 p.m. – 15:45 p.m. IST
Who: Rick O’Connor, RISC-V Foundation
To register for the event, please visit:
https://tmt.knect365.com/risc-v-workshop-chennai/purchase/select-package. To learn more about sponsorship opportunities, please visit:
https://tmt.knect365.com/risc-v-workshop-chennai/sponsor-book-stand.
For press interested in attending, please email:
risc-v@racepointglobal.com to receive your complimentary pass. To learn more about the RISC-V Foundation, its open, free architecture and membership information, please visit:
https://riscv.org.
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 100 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.
Contacts
Racepoint Global for RISC-V Foundation
Allison DeLeo, +1 415-694-6700
risc-v@racepointglobal.com